The present invention relates to a layout for an electric circuit of a semiconductor device that is formed on a substrate, such as a semiconductor chip, and a method for generating layout data for such an electric circuit. More particularly, the present invention relates to a pattern layout for a transistor and a method for generating layout data for a transistor.
FIG. 1 shows a layout for a metal oxide semiconductor (MOS) transistor. The MOS transistor is formed on a wafer in accordance with the layout. A diffusion region 1 has a bent portion bent at a right angle. The diffusion region 1 extends toward a well tap region (substrate contact region), a source-drain region of another transistor, or a connection node with a signal line or a power supply line etc.
A gate line 2, which is included in a polysilicon layer, overlaps part of the diffusion region 1. The gate line 2 extends perpendicularly to the diffusion region 1. Separate masks are used during exposure of the diffusion region 1 and the gate line 2. An exposure process and an etching process are performed on the diffusion region 1. Then, an exposure process and an etching process are performed on the gate line 2.
FIGS. 2A to 2C each show a diffusion region 3 and a gate line 4 that are formed on a wafer based on the layout shown in FIG. 1. The diffusion region 3 has an inner corner 5 that is rounded due to the exposure and etching.
FIG. 2A shows a gate line 4 that is formed at a desirable position. Since part of the gate line 4 overlaps a rounded inner corner 5 of the diffusion region 3, the gate line 4 has a gate width W+ΔW, which is greater than the desired gate width W shown in the state of FIG. 1.
As shown in FIG. 2B, a mask alignment error, or tolerance, may cause the gate line 4 to be formed at a position closer to the rounded inner corner 5. In this case, the increase in the overlapped part of the gate line 4 with the rounded inner corner 5 results in the gate line 4 having an increased gate width W+ΔW+α, which is greater than the gate width W+ΔW shown in the state of FIG. 2A.
As shown in FIG. 2C, a mask alignment error may cause the gate line 4 to be formed at a position farther from the rounded inner corner 5. In this case, the decrease in the overlapped part of the gate line 4 with the rounded inner corner 5 results in the gate line 4 having a decreased gate width W+Δ−α, which is less than the gate width W+ΔW shown in the state of FIG. 2A.
In this way, when the diffusion region 3 has the rounded inner corner 5, a mask alignment error would vary the gate width and change the transistor characteristics.
FIG. 3 shows the layout of another MOS transistor. A MOS transistor is formed on a wafer in accordance with the layout. A gate line 7 is overlapped with part of a straight portion of a diffusion region 6. The gate line 7 has a bent portion bent at a right angle. The gate line 7 extends toward a gate of another transistor or a connection node with another line.
FIGS. 4A to 4C each show a diffusion region 8 and a gate line 9 that are formed on a wafer based on the layout shown in FIG. 3. The gate line 9 has an inner corner 10 that is rounded due to exposure and etching.
FIG. 4A shows a gate line 9 that is formed at a desirable position. Since part of a rounded inner corner 10 of the gate line 9 overlaps a diffusion region 8, the gate line 9 has a gate length L+ΔL, which is greater than the desirable gate length L shown in the state of FIG. 3.
As shown in FIG. 4B, a mask alignment error may cause the rounded inner corner 10 of the gate line 9 to be formed at a position closer to the diffusion region 8. In this case, the increase in the overlapped part of the rounded inner corner 10 with the diffusion region 8 results in the gate line 9 having an increased gate length L+ΔL+α, which is greater than the gate length L+ΔL shown in the state of FIG. 4A.
As shown in FIG. 4C, a mask alignment error may cause the rounded inner corner 10 of the gate line 9 to be formed at a position farther from the diffusion region 8. In this case, the decrease in the overlapped part of the rounded inner corner 10 with the diffusion region 8 causes the gate line 9 having a decreased gate length L+ΔL−α, which is less than the gate length L+ΔL shown in the state of FIG. 4A.
In this way, when the gate line 9 has the rounded inner corner 10, a mask alignment error changes the gate width, and changes the transistor characteristics.